Informe Final - teisa

Curriculum Vitae:
Name: Fernando Herrera Casanueva
The format of this CV enables a first quick read in about 3 pages.
See annexes for a detailed description of sections 2 to 6. More information in:
www.teisa.unican.es/~fherrera
1. Personal Data:
Sex:
Male
Birth Date:
30-May-1975
Nationality:
Spanish
Contact data:
e-mail:
[email protected]
Phone:
+34 646 19 31 81
(mobile)
+34 942 94 30 34
(home)
Address:
C\ Av. San Martín del Pino 16, 18 - 4ºB
Santander (Cantabria),
C.P. 39005
Spain
Work:
e-mail:
[email protected]
Phone:
+34 942 20 08 78
Address:
TEISA Dpt.
E.T.S.I.I.T.
Av. Castros sn
C.P. 39005
Santander (Cantabria),
Spain
2. Titles:
PhD for the University of Cantabria (UC) with European Mention (Feb. 2009)
Master Degree: Telecommunication Eng. (Esp. Microelectronics) (June 2000, UC)
Degree: Telecommunication Tech. Eng. (Esp. Electronic Systems) (July 1997, UC)
3. Affiliations:
Member of the Spanish Association of Telecommunication Engineers
Member of IEEE
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4. Working Experience:
• Researcher of the Microelectronics Engineering Group (GIM) of the Electronics
Technology, Systems and Automation Engineering (TEISA) Department of the
University of Cantabria (UC). (11 years, from 1999, July up to now).
• Research as (UC PhD student) in the LECS/IMIT laboratory of the KTH
University in Stockholm (Sweeden) (3 months, 2004, October – 2004,
December).
• Tutor teacher of the Spanish Distance University (UNED), (3 years, from 2005,
Sept. to 2008, Sept).
• Assistant Professor of the UC for Bachellor Degree and Master Degree Courses
(3 years, from 2007, Sept. up to now).
• Preparation and teaching for several courses in the field of system-level
electronic design.
• Organization of project meetings, presentations and conference-related activities.
5. Merits:
• Award for the best Academic Expedient of Telecommunication Engineer of
the University of Cantabria.
• Publications (Book Chapters, Journals, and Conference Proceedings) with
international impact.
• Several merit-based educational Grants funded by the University of Cantabria
(UC), by UC/GIM, and by the Cantabria Regional Government.
6. Specific Formation:
• Attendance to different Courses, Workshops and Conferences, mostly on the
topic of Electronic Design, Electronic System-Level (ESL) electronic design
and design languages.
• Languages:
• SPANISH: Native
• ENGLISH: Advance Certificate. University of Cambridge.
• GERMAN : Goethe level 2.5
• FRENCH: High-School Certificate.
• Driving License (B Type). January 1998.
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7. Specific Know-How:
I have knowledge and experience on several topics, languages, toolkits and
environments, most of them related to system-level electronic design, embedded
system development, programming, and hardware development. The following bullets
give a summary of them:
•
System-Level specification in UML/MARTE and code generation within an
Eclipse based environment, and standard formats (UML/MARTE, XML, IP/XACT,
etc).
•
System-Level specification in SystemC and embedded software synthesis..
•
Knowledge about Models of Computation and Communication for Parallel
Programming (KPN, SDF, DDF, SR, etc) and related formalisms (ForSyDe).
•
Experience with development boards of several types:
§
Cross- development (ARM-based)
§
HW/SW development (with ARM-processor + Altera FPGAs)
§
SoC development (FPGA-based, including processor as a hard-IP core and
as a soft-IP core).
•
Embedded Systems cross-development environments: Mostly GNU-based
environments (g++, gdb,…), but also armcc.
•
EDA kits for HW design: ISE 11, Quartus-II, Synopsys (VSS, Behavioral
Compiler), Cadence (leapfrog), Tango, Orcad.
•
Hardware Description Languages: VHDL, Verilog, SystemC, (including
experience on description of synthesizable code).
•
Programming Languages: C++, C, Java, Ada, Pascal, LISP, Basic, Assembler
(Motorola, Intel, ARM, …).
•
System Specification and Code Generation Languages: SystemC, SpecC,
ImpulseC, UML, OCL, M2T, M (Matlab).
•
Host Operative Systems: Unix (Solaris), Linux (Ubuntu, Fedora, RedHat, Suse,
Mandriva), Windows (VISTA, XP, W2000, NT4.0, Wi98/95), MSDOS.
•
Office Packages (Microsoft, OpenOffice, etc), Academic Edition (LaTeX), and
other Desktop related software.
8. Aptitudes:
•
Motivation for Research, including deep knowledge of the practical and actual
state of art and search of innovative solutions.
•
Motivation for attendance to courses, workshops, tutorials, etc.
•
Motivation for learning and consolidation of Languages.
•
Experience in integration in team work and working in my own.
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•
•
Ready for public presentations, teaching and speech.
I like sport (field hockey, football, paddle, etc) and almost any cultural activity
(cinema, museums, etc). I was field Hockey player, several years as captain, of
Sardinero H.C. (8 years in the 1st division). I also used to draw, paint, an play
guitar.
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ANNEXES
2. Detail of Titles:
• PhD thesis: “Especificación Heterogénea y Generación Automática de Software
para Sistemas Embebidos desde SystemC” (Heterogeneous Specification and
Automatic Software Generation for Embedded Systems from SystemC).
Sobresaliente Cum Laude, with European Mention.
• Master Thesis of Telecommunication Engineer: "Especificación Reutilizable
para Codiseño de un Transmisor AAL-ATM", (Reusable Specification for Codesign
of an AAL-ATM transmitter). Maximum Qualification.
• Final Project for the degree of Telecommunication Engineer with 9,5: "Fuente
de alimentación variable controlada por entrada de tensión de muy alta
impedancia" (Adjustable power source controlled by very high impedance input).
3. Detail of Affiliations:
Member #9562 of the Spanish Association of Telecommunication Engineers
Member #80479923 (Region 8) of IEEE
4. Detail of the Working Experience:
Main Participation in Research Projects:
• Technical Responsible of UC/GIM in the IST FP7 European Project COdesing
and power Management in PLatform-based design space Exploration (COMPLEX,
http://complex.offis.de). UC/GIM is leader of WP2 in this project (December, 2009,
up to now).
• Technical Responsible of UC/GIM in the IST FP6 European Project Analysis and
Design of run-time Reconfigurable, heterogeneous Systems (ANDRES). (3 years,
2006, June – 2009, May).
• Contracted Researcher, as subcontractor for DS2, for the MEDEA+ A511 ToolIP
project. (2 years, 2002, January – 2003, December).
• Contracted Researcher of UC/GIM for TTI and Enyca local firms for the FEDERCICYT 1FD97-0791 project "Desarrollo de Metodologías Industriales de diseño de
Sistemas Embebidos Hw-Sw" (Development of Industrial Methodologies for the
design of HW/SW Embedded Systems). (1.5 years, 2000, July – 2001, December)
Others Related to Research
• Member of the Forum of Design Language (FDL) program commitee. (2 years,
2008, July – up to now)
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• Reviewer of the Forum of Design Language (FDL) and Design Automation and
Test in Europe Conference (DATE).
Teaching:
• Assistant Professor of the UC Computation Master Degree Courses (3 years,
from 2007, Sept. up to now) in the subjects of Languages and Tools for
SystemcSpecification and Design, and HW/SW Co-Design.
• Assistant Professor of the subject Especification and Co-Design of Electronic
Systems of the last course of the UC Informatics Degree in the subjects of
Languages and Tools for SystemcSpecification and Design, and HW/SW CoDesign. (1 years, from 2009, Sept. up to now)
• Tutor teacher of the Spanish Distance University (UNED), (3 years, from 2005,
Sept. to 2008, Sept) in electronic related subjects (Basic Electronics, Digital
Electronics, Electronic Components and Circuits, etc).
• Speaker in the ECSI Workshop (www.ecsi.org) "UML profiles for Embedded
Systems”. Paris. March. 27-87, 2006.
• Teacher of “SystemC laboratory” and Lecturer about “Embedded Software
Generation”, at the course "Especificación y Análisis de Sistemas en SystemC.
Generación de HW y SW", in the cycle “Co-Diseño de HW/SW”. LEIOA. Univ. del
País Vasco. Feb. 25-27, 2004.
• Preparation and teaching of a laboratory class for the summer course "Diseño
de Sistemas Embebidos HW/SW", (Design of HW/SW Embedded Systems). Univ.
Of Cantabria, July 2001.
• Assistant in the organization of DATE’06, DATE’04 and DCIS’02 International
conferences, dedicated to electronic design.
• Preparation of material for DATE’08 tutorial F1 “Heterogeneous System-Level
Specification using SystemC: System Specification in SystemC/HetSC”. Munich,
March 2008
• Preparation of material for ARTIS2 Workshop on Models of Computation and
Communication (MoCC'06), "SystemC as an Heterogeneous System Specification
Language" ETH, Zurich. 2006.
• Speaker in international conferences (FDL, DAC, DCIS).
• In charge of GIM/UC demo in University Booth in DAC’06.
5. Detail of Merits:
• Award for the best Academic Expedient of Telecommunication Engineer of the
University of Cantabria, (8,013), Course 2000.
• Main Grants:
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o Post-Doc grant funded by the UC (1 year)
o PhD Grant funded by Cantabria Government UC/GIM (4 years, 2002, April –
2006, March)
o Grant funded by UC for working as UC PhD student in the LECS/IMIT
laboratory of the KTH University in Stockholm (Sweeden).
o Grant funded by GIM/UC as researcher student (1 year, course 1999/2000).
Publications
Book chapters:
• F. Herrera, E. Villar, C.Grimm, M.Damm, J.Haase. "Heterogeneous Specification
with HetSC and SystemC-AMS. Widening the support of MoCs in SystemC". E.
Villar (Ed.): "Embedded Systems Specification and Design Languages", The CHDL
Series V.10, Springer, pp-107-121. 2008-06.
• F.Herrera and E.Villar. “Mixing Synchronous Reactive and Untimed Models of
Computation in SystemC” in Ed. A.Vauchoux (Eds) “Advances in Design and
Specification Languages for SoCs”. Kluwer, 2006.
• F.Herrera, P.Sánchez and E.Villar. “Heterogeneous System-Level Specification in
SystemC” in Ed. P. Boulet (Eds) “Advances in Design and Specification Languages
for SoCs”. Kluwer, 2005.
• F.Herrera, P.Sánchez, E.Villar. “Modeling and Design of CSP, KPN, and SR
Systems with SystemC”, pg 133-148 in Christoph Grimm (Editor.) "Languages for
System Specification" CHDL Series Kluwer, 2004.
• F.Herrera, H.Posadas, P.Sánchez and E.Villar. “Systematic Embedded Software
Generation from SystemC”, in A.Jerraya, S.Yoo, D.Verkest&N.When
(Eds):”Embedded Software for SoC”, Kluwer, 2003, press.
• V.Fernández, F.Herrera, P.Sánchez and E.Villar. Chapter “Embedded Software
Generation From SystemC For Platform Based Design” in “SystemC:
Methodologies and Applications”. Ed. W.Mueller, W. Rosenstiel, J.Ruf. Kluwer
Academic Publishers. March 2003.
• V.Fernández and F.Herrera. Chapter “Introduction to SystemC” in “Design of
Hardware/Software Embedded Systems”. Ed. E.Villar. Publishing Services of the
University of Cantabria.2001.
Journals:
• J. Haase, M. Damm, C. Grimm, F. Herrera, E. Villar. "Bridging MoCs in SystemC
Specifications of Heterogeneous Systems". EURASIP Journal on Embedded Systems, Special Issue "C-Based Design of Heterogeneous Embedded Systems",
Volume 2008 (2008), Article ID 738136, 16 pages. 2008-05.
• F. Herrera and E. Villar. "A Framework for Heterogeneous Specification and Design
of Electronic Embedded Systems in SystemC". ACM Transactions on Design Auto-
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mation of Electronic Systems, Special Issue on Demonstrable Software Systems
and Hardware Platforms, V.12, Issue 3, N.22. 2007-08.
• H.Posadas, F.Herrera, V.Fernández, P.Sánchez, E.Villar&F.Blasco. “Single-Source
Design Environment for Embedded Systems based on SystemC”. Journal on
Design Automation for Embedded Systems. Springer. 2005.
Papers:
• P. Peñil, F. Herrera, E. Villar. "Formal Foundations for MARTE-SystemC
Interoperability" Forum on specification & Design Languages 2010, FDL'2010.
Southampton, UK. 2010.
• V. Fernández, F. Herrera, E. Villar. "Formal Support for Untimed SystemC
specifications: Application to high-level synthesis". Forum on specification & Design
Languages 2010, FDL'2010. Southampton, UK. 2010.
• F. Herrera and E. Villar. "Local Application of Simulation Directed for Exhaustive
Coverage of Schedulings in SystemC Specifications". Proceedings of the Forum on
specification and Design Languages, FDL'09, IEEE 2009. ISSN: 1636-9874. 200909.
• F. Herrera, E. Villar and P. A. Hartmann. "Specification of HW/SW adaptive
Embedded Systems in SystemC". Proceedings of the Forum on specification and
Design Languages, FDL'08, IEEE, 2008. 2008-09.
• J. Haase, M. Damm, C. Grimm, F. Herrera, E. Villar. "Using Converter Channels
within a Top-Down Design Flow in SystemC". The 15th Austrian Workhop on
Microelectronics, Graz, Austria. 2007-10.
• F. Herrera, E. Villar, C. Grimm, M. Damm, J. Haase. "A general approach to the
interoperability of HetSC and SystemC-AMS". Proceedings of the Forum on Design
Languages 2007, FDL'07. Barcelona. 2007-09.
• A.Herrholz, F. Oppenheimer, P.A.Hartmann, A.Schallenberg, W. Nebel, C.Grimm,
M.Damm, J.Haase, F.Brame, F. Herrera, E. Villar, I.Sander, A. Jantsch,
A.M.Foulliart, M.Martínez. "The ANDRES project: Analysis and Design of Run-time
REconfigurable, heterogeneous Systems". 17 th International Conference on Field
Programmable Logic and Applications. Amsterdam. 2007-08
• A. Herrholz, F. Oppenheimer, A. Schallenberg, W. Nebel, C. Grimm, M. Damm, F.
Herrera, E. Villar, A-M. Fouilliart and M. Martínez. "ANDRES ANalysis and Design
of run-time REconfigurable, heterogeneous Systems". Workshop on "Adaptive
Heterogeneous Systems-On-Chip and European Dimensions" in the Design
Automation and Test in Europe 2007, DATE'07. 2007-04.
• E.Villar and F.Herrera. “SystemC as an Heterogeneous System Specification
Language”. ARTIST2 Workshop on Models of Computation and Communication
(MoCC'06), ETH, Zurich. 2006-11.
• F.Herrera and E.Villar. “Extension of the SystemC kernel for Simulation Coverage
Improvement of System-Level Concurrent Specifications”. FDL’06, Darmstadt, Sept.
2006.
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• F.Herrera and Villar. “A Framework for Embedded System Specification under
Different Models of Computation in SystemC”. DAC’06, San Francisco, Jul. 2006.
• F.Herrera and E.Villar. “Mixing Synchronous Reactive and Untimed Models of
Computation in SystemC”. FDL’05, Laussane, Sept. 2005.
• F.Herrera,P.Sanchez, E.Villar. “Heterogeneous System-Level Specification in
SystemC”. FDL’04, Lille ,13-17 Sept. 2004.
• H.Posadas, F.Herrera, P.Sánchez and E.Villar.(Univ. Cantabria) & F.Blasco.
“System-Level Performance Analysis in SystemC”. DATE’04, Paris, 16-20 Feb.2004
• F.Herrera, P.Sánchez, E.Villar. “Modeling of CSP, KPN and SR Systems with
SystemC”. FDL’03, Frankfurt ,23-26 Sept. 2003.
• F.Herrera, H.Posadas, P.Sánchez, E.Villar. “Systematic Embedded Software
Generation from SystemC”. DATE03, Munich, 3-7 March. .
• F.Blasco, E.Villar and F.Herrera. “System-Level Dynamic Estimation of Time
Performance for Codesign based on SystemC and HW/SW platform”. DCIS’02,
Santander, November 19-22. 2002.
• F.Herrera, P.Sánchez, E.Villar. "HW/SW Interface Implementation from SystemC for
Platform Based Design", FDL’02, Marseille 26-29 Sept. 2002.
• E.Villar y F.Herrera. “SystemC-Level specification in SystemC of
Gateway”. DCIS’01 Oct. 2001.
a Residential
• E.Villar, C.I. Camargo and.Herrera. "Embedded Systems Design Methodology
based on SystemC", FDL’01, Lyon 3-7 Sept. 2001.
• F.Herrera, R.Rodríguez, V.Fernández, P.Sánchez y E.Villar. "Desarrollo de
Metodologías Industriales de Diseño de Sistemas Embebidos Hw/Sw", TEDEA.
Septiembre 2000. Ciudad Real.
• F.Herrera, C.Sanz, I.Ugarte y E. Villar. "Specification components: reusability at the
HW/SW system specification level", In “Soft Cores, Reuse and Systems
Integration". Proc. VIUF’99 Orlando, Florida, October 1999.
Project Related Documentation:
• S. Real, F. Herrera, Eugenio Villar. "Modelling of SW. Final library elements.". Deliverable D1.2b of the ANDRES project. 2009-01.
• F.Oppenheimer, K.Gruettner, A. Jantsch, F. Colas-Bigey, J. Haase, M. Martinez,
Fernando Herrera, Eugenio Villar. "Intermediate Dissemination and Demonstration
Plan". Deliverable D4.1c of the ANDRES project. 2008-07.
• J. Haase, P. A. Hartmann, F. Herrera. "Initial Version of Integrated Framework." Deliverable D1.6a of the ANDRES project. 2008-06.
• K.Gruettner, A. Herrholz, P. A. Hartmann, Fernando Herrera, E. Villar. "Interface
Synthesis Concept". Deliverable D2.3a of the ANDRES project. 2008-06.
• F. Herrera, E. Villar. "Modeling of Software. Initial Library elements". Deliverable
D1.2a of the IST 5-033511 ANDRES Project. 2007, June.
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• F. Herrera, E. Villar, C. Grimm (TUV), I. Sander (KTH), A. Jantsch (KTH). "Methodology for Specification of Adaptivity". D1.1 Deliverable of the ANDRES IST-5-033511
Project. 2006-11.
• H.Posadas, F.Herrera, P.Sánchez and E.Villar. ”Library for Microprocessor Core
Analysis. Users Guide”. UC/ToolIP/IR/02 Internal Report of the MEDEA+ ToolIP
project. (Authorized by F.Blasco, DS2). December, 2002.
• H.Posadas, F.Herrera, P.Sánchez and E.Villar. “Library for Microprocessor Core
Analysis”. Final Deliverable DS2-T1.3-Q4/02. UC/ToolIP/IR/02 Internal Report of the
MEDEA+ project. (Authorized by F.Blasco, DS2). December, 2002.
• H.Posadas, F.Herrera, P.Sánchez and E.Villar. “Documento de requisitos técnicos
de la biblioteca de perfilado”. DS2-T1.3-Q4/02. UC/ToolIP/IR/03 Internal Report of
the ToolIP MEDEA+ project. (Authorized by F.Blasco, DS2). November, 2002.
• F.Herrera, P.Sánchez and E.Villar. “First Draft of the Library for Microprocessor
Core Analysis”. (Authorized by F..Blasco, DS2). Santander. Internal Report of the
ToolIP MEDEA+ project. June, 2002.
• F.Herrera, P.Sánchez and E.Villar. “Comparative study for the selection of the
processor core analysis”. UC/ToolIP/IR/02 Internal Report of the ToolIP MEDEA+
project (Authorized by F.Blasco, DS2). Santander. June, 2002.
• V.Fernández, F.Herrera, P.Sánchez y E.Villar. “Conclusiones: Metodología
Industrial de Diseño de Sistemas Embebidos HW/SW”, Documento entregable DF
del proyecto FEDER "Desarrollo de Metodologías Industriales de Diseño de
Sistemas Embebidos Hw/Sw",. Febrero 2002. Universidad de Cantabria.
• V.Fernández, F.Herrera y E.Villar. “Especificación Ejecutable del Demostrador
Industrial", Documento entregable R2-C2 del proyecto FEDER "Desarrollo de
Metodologías Industriales de Diseño de Sistemas Embebidos Hw/Sw". 2001, Abril.
Universidad de Cantabria.
• F.Herrera, V.Fernández, R.Rodríguez, P.Sánchez y E.Villar. “Especificación del
Demostrador Industrial", Documento entregable R2-C1 del proyecto FEDER
"Desarrollo de Metodologías Industriales de Diseño de Sistemas Embebidos
Hw/Sw". 2000, Octubre. Universidad de Cantabria.
6. Details on Specific Formation:
PhD courses. 2000-2001. TEISA Dpt. University of Cantabria, (210 hours):
Design Tools, Design of HW/SW embedded systems, Verification of Embedded
Systems, Test of VLSI digital systems, Structured Design for Test, Concurrent
Programming, and Programming in the JAVA language.
Specific Courses
• Advanced Course on the Development of Linux-based Embedded Systems. In the
Universidad Autónoma of Madrid, UAM. 2008, March. 24 hours.
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• Webminar for Design of Algorithms and Code Generation with Embedded Matlab.
• Course “Tutor Telemático de la UNED” (Ability to use as tutor professor the different
e-learning tools of UNED, i.e. WebCT), 2006/07.
• “La Convergencia Digital”. Summer Course of the University of Cantabria. July 1214th, 2005. Laredo. Spain. 30 hours.
• "Diseño de Sistemas Embebidos HW/SW". University of Cantabria. 2-6th July 2001.
30 hours.
• Course of System on Chips. TIMA Laboratory. University of Grenoble, Grenoble.
May, 2000. 20 hours.
• “Mathematica”. Applied Mathematics and Computing Sciences Department of the
University of Cantabria. Diciembre 1996. 16 horas. Santander.
Attendance to Conferences, Workshops and Tutorials:
• Forum of Design Languages, (FDL’09). September, 2009. Sophia-Antipolis.
• Design, Automation and Test in Europe, DATE’09. Nice, France. April, 2009.
• Forum of Design Languages, (FDL’08). September, 2008. Stuttgart.
• Forum of Design Languages, (FDL’07). September, 2007. Barcelona.
• ECSI Workshop on Reconfigurable Systems-on-Chip. March, 2007. Paris.
• Forum of Design Languages, (FDL’06). September 2006. Darmstadt.
• ECSI&UBS Workshop on High-Level Synthesis. September 18th. 2006. Darmstadt.
• Design Automation Conference 2006 (DAC’06). September, 2006. San Francisco.
• Embedded Linux Seminar. Bilbao, Spain. June, 2006.
• ECSI Workshop on UML Profiles for Embedded Systems. March, 2006. Paris.
• 13th SystemC Users Group (SCUG) Meeting. March, 2006. Paris.
• Design, Automation and Test in Europe, DATE’06. Tutorials, Exhibitions and Master
Course. March 6-10. Munich.
• Forum of Design Languages, (FDL’05). September 2005. Laussane.
• 12th SystemC Users Group (SCUG) Meeting. September, 2005. Laussane.
• ECSI Synthesis Workshop. 13th September. 2004. Lille.
• FDL'04. 14-17th September 2004. Lille.
• DATE’04. Tutorials, Exhibitions and Master Course.16-20 February. Paris.
• 9th SCUG Meeting. February 17th. Paris.
• DCIS'02. November. 2002. Santander.
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• FDL’02. 26-29 Sept. 2002. Marseille.
• Workshop of MEDEA+ Toolip project. May, 2002. Paris.
• FDL’01. 3-7 September. 2001. Lyon.
• DATE’01conference. Tutorials and Exhibitions. March, 2001. Munich.
• 3rd SCUG Meeting. March, 2001. Munich.
• 2nd SystemC meeting. June 2000, Munich.
(Project related workshops and tutorials not included)
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