Core Messaging deck “Data Access – A New Approach”

Core Messaging deck “Data Access – A New Approach”

Data Access—A New Approach
October 11, 2016
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© Gen-Z Consortium 2016
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Gen-Z Consortium
• Industry Leaders developing a memory-semantic interconnect
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Why Propose a New Bus?
Explosive Growth of Data
• System memory is flat or shrinking
• Memory bandwidth per core continues to decrease
• Memory capacity per core is generally flat
• Memory is changing on a different cadence compared to
the CPU
2015
2005 2010
0.1ZB 1.2ZB
2.8ZB
8.5ZB
• Data is growing
• More than 37% of total data generated in
2020 (40 ZB) will have Big Data value
• Data that requires real-time analysis is growing
exponentially
• The value of the analysis decreases if it takes too long to
provide insights
Need Answers … FAST!
• The industry needs an open architecture to solve the
problems
10-2
100
102
104
106
Seconds
Time to Result
•
•
© Gen-Z Consortium 2016
Value of Analyzed Data
$
• Memory tiers will become increasingly important
• Rack-scale composability requires a high bandwidth, low
latency fabric
• Must seamlessly plug into existing ecosystems without
requiring OS changes
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2020
40
ZB
2012
Businesses demanding real-time insight
Increasing amounts of data to be analyzed
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Memory/Storage Convergence: The Media Revolution
Today
Memory
DRAM
DRAM
SCM*
Storage
Disk/SSD
Disk/SSD
Memory Semantics will be pervasive in Volatile AND NonVolatile Storage as these technologies continue to converge.
*SCM = Storage Class Memory
**OPM = On-Package Memory
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DRAM/OPM**
SCM*
DRAM/OPM**
SCM*
Disk/SSD
Disk/SSD
New and Emerging Memory Technologies
HMC
3DXPointTM
Memory
HBM
MRAM
Low
Latency
NAND
PCM
Managed
DRAM
RRAM
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Memory-Semantic Fabric
• Communication at the speed of Memory
What is a Memory Semantic Fabric?
• Handles all communication as memory operations
such as load/store, put/get and atomic operations
typically used by a processor
Compute
SoC
SoC
Memory
Memory
Accelerators
FPGA
FPGA
GPU
GPU
Memory
Memory
• Memory semantics are optimal at sub-microsecond
latencies from CPU load command to register store
• Unlike, storage accesses which are block based and
managed by complex, code intensive, software stacks
Memory Semantics
Why Now?
• The emergence of low latency, Storage Class
Memory (SCM) and the demand for large capacity,
rack scale resource pools, and multi node
architectures
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© Gen-Z Consortium 2016
Pooled Memory
Network
Storage
I/O
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Gen-Z: A New Data Access Technology
High
Bandwidth
Low Latency
Advanced
Workloads
&
Technologies
− Memory Semantics – simple Reads and
Writes
− From tens to several hundred GB/s of
bandwidth
Compute
− Sub-100 ns load-to-use memory latency
SoC
SoC
− Real time analytics
Memory
Memory
Accelerators
FPGA
FPGA
GPU
GPU
Memory
Memory
− Enables data centric and hybrid computing
− Scalable memory pools for in memory
applications
− Abstracts media interface from SoC to
unlock new media innovation
Gen-Z Direct Attach, Switched, or Fabric Topology
− Provides end-to-end secure connectivity
from node level to rack scale
Secure
Compatible
Economical
− Supports unmodified OS for SW
compatibility
Pooled Memory
− Graduated implementation from simple,
low cost to highly capable and robust
− Leverages high-volume IEEE physical
layers and broad, deep industry ecosystem
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© Gen-Z Consortium 2016
Network
Storage
I/O
Rack Scale
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Gen-Z Consortium
Mission
• Create a next generation interconnect that will bridge
existing solutions while enabling new unbounded
innovation
• Develop in an open, non-proprietary standards body
where adoption, differentiation and innovation is
promoted as an industry standard.
Board Members
A Transparent Organization: Gen-Z has been formed as a not-for-profit organization, its ongoing development
occurs on the basis of an open decision-making procedure available to all interested parties.
Wide availability: The Gen-Z standard will be published and available free of charge.
End-User Choice: There are no constraints on the re-use of the standard. Gen-Z creates a fair, competitive
market for implementations of the standard.
Equality: Gen-Z does not favor one implementer over another.
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